@web-font-path: "roboto-debian.css";
Menu Toggle
v1.5.1
Loading...
Searching...
No Matches
mpu.h
1
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
3
/*
4
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
5
*
6
* SPDX-License-Identifier: BSD-3-Clause
7
*/
8
9
#ifndef _HARDWARE_STRUCTS_MPU_H
10
#define _HARDWARE_STRUCTS_MPU_H
11
12
#include "
hardware/address_mapped.h
"
13
#include "hardware/regs/m0plus.h"
14
15
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
16
//
17
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
18
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
19
//
20
// Bit-field descriptions are of the form:
21
// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
22
23
typedef
struct
{
24
_REG_(M0PLUS_MPU_TYPE_OFFSET)
// M0PLUS_MPU_TYPE
25
// Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports
26
// 0x00ff0000 [23:16] : IREGION (0): Instruction region
27
// 0x0000ff00 [15:8] : DREGION (0x8): Number of regions supported by the MPU
28
// 0x00000001 [0] : SEPARATE (0): Indicates support for separate instruction and data address maps
29
io_ro_32 type;
30
31
_REG_(M0PLUS_MPU_CTRL_OFFSET)
// M0PLUS_MPU_CTRL
32
// Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled...
33
// 0x00000004 [2] : PRIVDEFENA (0): Controls whether the default memory map is enabled as a background region for...
34
// 0x00000002 [1] : HFNMIENA (0): Controls the use of the MPU for HardFaults and NMIs
35
// 0x00000001 [0] : ENABLE (0): Enables the MPU
36
io_rw_32 ctrl;
37
38
_REG_(M0PLUS_MPU_RNR_OFFSET)
// M0PLUS_MPU_RNR
39
// Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR
40
// 0x0000000f [3:0] : REGION (0): Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers
41
io_rw_32 rnr;
42
43
_REG_(M0PLUS_MPU_RBAR_OFFSET)
// M0PLUS_MPU_RBAR
44
// Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR
45
// 0xffffff00 [31:8] : ADDR (0): Base address of the region
46
// 0x00000010 [4] : VALID (0): On writes, indicates whether the write must update the base address of the region...
47
// 0x0000000f [3:0] : REGION (0): On writes, specifies the number of the region whose base address to update provided...
48
io_rw_32 rbar;
49
50
_REG_(M0PLUS_MPU_RASR_OFFSET)
// M0PLUS_MPU_RASR
51
// Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region...
52
// 0xffff0000 [31:16] : ATTRS (0): The MPU Region Attribute field
53
// 0x0000ff00 [15:8] : SRD (0): Subregion Disable
54
// 0x0000003e [5:1] : SIZE (0): Indicates the region size
55
// 0x00000001 [0] : ENABLE (0): Enables the region
56
io_rw_32 rasr;
57
}
mpu_hw_t
;
58
59
#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
60
61
#endif
address_mapped.h
mpu_hw_t
Definition
mpu.h:23