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iobank0.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
3/*
4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _HARDWARE_STRUCTS_IOBANK0_H
10#define _HARDWARE_STRUCTS_IOBANK0_H
11
13#include "hardware/regs/io_bank0.h"
14
15// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
16//
17// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
18// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h.
19//
20// Bit-field descriptions are of the form:
21// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
22
23typedef struct {
24 _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS
25 // GPIO status
26 // 0x04000000 [26] : IRQTOPROC (0): interrupt to processors, after override is applied
27 // 0x01000000 [24] : IRQFROMPAD (0): interrupt from pad before override is applied
28 // 0x00080000 [19] : INTOPERI (0): input signal to peripheral, after override is applied
29 // 0x00020000 [17] : INFROMPAD (0): input signal from pad, before override is applied
30 // 0x00002000 [13] : OETOPAD (0): output enable to pad after register override is applied
31 // 0x00001000 [12] : OEFROMPERI (0): output enable from selected peripheral, before register override is applied
32 // 0x00000200 [9] : OUTTOPAD (0): output signal to pad after register override is applied
33 // 0x00000100 [8] : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied
34 io_ro_32 status;
35
36 _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL
37 // GPIO control including function select and overrides
38 // 0x30000000 [29:28] : IRQOVER (0)
39 // 0x00030000 [17:16] : INOVER (0)
40 // 0x00003000 [13:12] : OEOVER (0)
41 // 0x00000300 [9:8] : OUTOVER (0)
42 // 0x0000001f [4:0] : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table
43 io_rw_32 ctrl;
45
46typedef struct {
47 _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0
48 // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
49 //
50 // Interrupt Enable for proc0
51 // 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
52 // 0x40000000 [30] : GPIO7_EDGE_LOW (0)
53 // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
54 // 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
55 // 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
56 // 0x04000000 [26] : GPIO6_EDGE_LOW (0)
57 // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
58 // 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
59 // 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
60 // 0x00400000 [22] : GPIO5_EDGE_LOW (0)
61 // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
62 // 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
63 // 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
64 // 0x00040000 [18] : GPIO4_EDGE_LOW (0)
65 // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
66 // 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
67 // 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
68 // 0x00004000 [14] : GPIO3_EDGE_LOW (0)
69 // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
70 // 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
71 // 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
72 // 0x00000400 [10] : GPIO2_EDGE_LOW (0)
73 // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
74 // 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
75 // 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
76 // 0x00000040 [6] : GPIO1_EDGE_LOW (0)
77 // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
78 // 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
79 // 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
80 // 0x00000004 [2] : GPIO0_EDGE_LOW (0)
81 // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
82 // 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
83 io_rw_32 inte[4];
84
85 _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0
86 // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
87 //
88 // Interrupt Force for proc0
89 // 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
90 // 0x40000000 [30] : GPIO7_EDGE_LOW (0)
91 // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
92 // 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
93 // 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
94 // 0x04000000 [26] : GPIO6_EDGE_LOW (0)
95 // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
96 // 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
97 // 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
98 // 0x00400000 [22] : GPIO5_EDGE_LOW (0)
99 // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
100 // 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
101 // 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
102 // 0x00040000 [18] : GPIO4_EDGE_LOW (0)
103 // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
104 // 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
105 // 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
106 // 0x00004000 [14] : GPIO3_EDGE_LOW (0)
107 // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
108 // 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
109 // 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
110 // 0x00000400 [10] : GPIO2_EDGE_LOW (0)
111 // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
112 // 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
113 // 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
114 // 0x00000040 [6] : GPIO1_EDGE_LOW (0)
115 // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
116 // 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
117 // 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
118 // 0x00000004 [2] : GPIO0_EDGE_LOW (0)
119 // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
120 // 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
121 io_rw_32 intf[4];
122
123 _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0
124 // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
125 //
126 // Interrupt status after masking & forcing for proc0
127 // 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
128 // 0x40000000 [30] : GPIO7_EDGE_LOW (0)
129 // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
130 // 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
131 // 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
132 // 0x04000000 [26] : GPIO6_EDGE_LOW (0)
133 // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
134 // 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
135 // 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
136 // 0x00400000 [22] : GPIO5_EDGE_LOW (0)
137 // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
138 // 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
139 // 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
140 // 0x00040000 [18] : GPIO4_EDGE_LOW (0)
141 // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
142 // 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
143 // 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
144 // 0x00004000 [14] : GPIO3_EDGE_LOW (0)
145 // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
146 // 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
147 // 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
148 // 0x00000400 [10] : GPIO2_EDGE_LOW (0)
149 // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
150 // 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
151 // 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
152 // 0x00000040 [6] : GPIO1_EDGE_LOW (0)
153 // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
154 // 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
155 // 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
156 // 0x00000004 [2] : GPIO0_EDGE_LOW (0)
157 // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
158 // 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
159 io_ro_32 ints[4];
161
163typedef struct {
164 iobank0_status_ctrl_hw_t io[NUM_BANK0_GPIOS]; // 30
165
166 _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0
167 // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
168 //
169 // Raw Interrupts
170 // 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
171 // 0x40000000 [30] : GPIO7_EDGE_LOW (0)
172 // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
173 // 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
174 // 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
175 // 0x04000000 [26] : GPIO6_EDGE_LOW (0)
176 // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
177 // 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
178 // 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
179 // 0x00400000 [22] : GPIO5_EDGE_LOW (0)
180 // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
181 // 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
182 // 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
183 // 0x00040000 [18] : GPIO4_EDGE_LOW (0)
184 // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
185 // 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
186 // 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
187 // 0x00004000 [14] : GPIO3_EDGE_LOW (0)
188 // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
189 // 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
190 // 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
191 // 0x00000400 [10] : GPIO2_EDGE_LOW (0)
192 // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
193 // 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
194 // 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
195 // 0x00000040 [6] : GPIO1_EDGE_LOW (0)
196 // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
197 // 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
198 // 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
199 // 0x00000004 [2] : GPIO0_EDGE_LOW (0)
200 // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
201 // 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
202 io_rw_32 intr[4];
203
204 io_irq_ctrl_hw_t proc0_irq_ctrl;
205
206 io_irq_ctrl_hw_t proc1_irq_ctrl;
207
208 io_irq_ctrl_hw_t dormant_wake_irq_ctrl;
210
211#define iobank0_hw ((iobank0_hw_t *)IO_BANK0_BASE)
213
214static_assert( NUM_BANK0_GPIOS == 30, "");
215
216#endif
Definition iobank0.h:46
Definition iobank0.h:163
Definition iobank0.h:23