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spi.h
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1/*
2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef _HARDWARE_SPI_H
8#define _HARDWARE_SPI_H
9
10#include "pico.h"
11#include "hardware/structs/spi.h"
12#include "hardware/regs/dreq.h"
13
14// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SPI, Enable/disable assertions in the SPI module, type=bool, default=0, group=hardware_spi
15#ifndef PARAM_ASSERTIONS_ENABLED_SPI
16#define PARAM_ASSERTIONS_ENABLED_SPI 0
17#endif
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
38// PICO_CONFIG: PICO_DEFAULT_SPI, Define the default SPI for a board, min=0, max=1, group=hardware_spi
39// PICO_CONFIG: PICO_DEFAULT_SPI_SCK_PIN, Define the default SPI SCK pin, min=0, max=29, group=hardware_spi
40// PICO_CONFIG: PICO_DEFAULT_SPI_TX_PIN, Define the default SPI TX pin, min=0, max=29, group=hardware_spi
41// PICO_CONFIG: PICO_DEFAULT_SPI_RX_PIN, Define the default SPI RX pin, min=0, max=29, group=hardware_spi
42// PICO_CONFIG: PICO_DEFAULT_SPI_CSN_PIN, Define the default SPI CSN pin, min=0, max=29, group=hardware_spi
43
47typedef struct spi_inst spi_inst_t;
48
55#define spi0 ((spi_inst_t *)spi0_hw)
56
63#define spi1 ((spi_inst_t *)spi1_hw)
64
65#if !defined(PICO_DEFAULT_SPI_INSTANCE) && defined(PICO_DEFAULT_SPI)
66#define PICO_DEFAULT_SPI_INSTANCE (__CONCAT(spi,PICO_DEFAULT_SPI))
67#endif
68
69#ifdef PICO_DEFAULT_SPI_INSTANCE
70#define spi_default PICO_DEFAULT_SPI_INSTANCE
71#endif
72
76typedef enum {
77 SPI_CPHA_0 = 0,
78 SPI_CPHA_1 = 1
80
84typedef enum {
85 SPI_CPOL_0 = 0,
86 SPI_CPOL_1 = 1
88
92typedef enum {
93 SPI_LSB_FIRST = 0,
94 SPI_MSB_FIRST = 1
96
97// ----------------------------------------------------------------------------
98// Setup
99
112uint spi_init(spi_inst_t *spi, uint baudrate);
113
121void spi_deinit(spi_inst_t *spi);
122
133uint spi_set_baudrate(spi_inst_t *spi, uint baudrate);
134
143uint spi_get_baudrate(const spi_inst_t *spi);
144
151static inline uint spi_get_index(const spi_inst_t *spi) {
152 invalid_params_if(SPI, spi != spi0 && spi != spi1);
153 return spi == spi1 ? 1 : 0;
154}
155
156static inline spi_hw_t *spi_get_hw(spi_inst_t *spi) {
157 spi_get_index(spi); // check it is a hw spi
158 return (spi_hw_t *)spi;
159}
160
161static inline const spi_hw_t *spi_get_const_hw(const spi_inst_t *spi) {
162 spi_get_index(spi); // check it is a hw spi
163 return (const spi_hw_t *)spi;
164}
165
177static inline void spi_set_format(spi_inst_t *spi, uint data_bits, spi_cpol_t cpol, spi_cpha_t cpha, __unused spi_order_t order) {
178 invalid_params_if(SPI, data_bits < 4 || data_bits > 16);
179 // LSB-first not supported on PL022:
180 invalid_params_if(SPI, order != SPI_MSB_FIRST);
181 invalid_params_if(SPI, cpol != SPI_CPOL_0 && cpol != SPI_CPOL_1);
182 invalid_params_if(SPI, cpha != SPI_CPHA_0 && cpha != SPI_CPHA_1);
183
184 // Disable the SPI
185 uint32_t enable_mask = spi_get_hw(spi)->cr1 & SPI_SSPCR1_SSE_BITS;
186 hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS);
187
188 hw_write_masked(&spi_get_hw(spi)->cr0,
189 ((uint)(data_bits - 1)) << SPI_SSPCR0_DSS_LSB |
190 ((uint)cpol) << SPI_SSPCR0_SPO_LSB |
191 ((uint)cpha) << SPI_SSPCR0_SPH_LSB,
192 SPI_SSPCR0_DSS_BITS |
193 SPI_SSPCR0_SPO_BITS |
194 SPI_SSPCR0_SPH_BITS);
195
196 // Re-enable the SPI
197 hw_set_bits(&spi_get_hw(spi)->cr1, enable_mask);
198}
199
209static inline void spi_set_slave(spi_inst_t *spi, bool slave) {
210 // Disable the SPI
211 uint32_t enable_mask = spi_get_hw(spi)->cr1 & SPI_SSPCR1_SSE_BITS;
212 hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS);
213
214 if (slave)
215 hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS);
216 else
217 hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS);
218
219 // Re-enable the SPI
220 hw_set_bits(&spi_get_hw(spi)->cr1, enable_mask);
221}
222
223// ----------------------------------------------------------------------------
224// Generic input/output
225
232static inline bool spi_is_writable(const spi_inst_t *spi) {
233 return (spi_get_const_hw(spi)->sr & SPI_SSPSR_TNF_BITS);
234}
235
242static inline bool spi_is_readable(const spi_inst_t *spi) {
243 return (spi_get_const_hw(spi)->sr & SPI_SSPSR_RNE_BITS);
244}
245
252static inline bool spi_is_busy(const spi_inst_t *spi) {
253 return (spi_get_const_hw(spi)->sr & SPI_SSPSR_BSY_BITS);
254}
255
268int spi_write_read_blocking(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len);
269
281int spi_write_blocking(spi_inst_t *spi, const uint8_t *src, size_t len);
282
298int spi_read_blocking(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, size_t len);
299
300// ----------------------------------------------------------------------------
301// SPI-specific operations and aliases
302
303// FIXME need some instance-private data for select() and deselect() if we are going that route
304
319int spi_write16_read16_blocking(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len);
320
334int spi_write16_blocking(spi_inst_t *spi, const uint16_t *src, size_t len);
335
353int spi_read16_blocking(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len);
354
361static inline uint spi_get_dreq(spi_inst_t *spi, bool is_tx) {
362 static_assert(DREQ_SPI0_RX == DREQ_SPI0_TX + 1, "");
363 static_assert(DREQ_SPI1_RX == DREQ_SPI1_TX + 1, "");
364 static_assert(DREQ_SPI1_TX == DREQ_SPI0_TX + 2, "");
365 return DREQ_SPI0_TX + spi_get_index(spi) * 2 + !is_tx;
366}
367
368#ifdef __cplusplus
369}
370#endif
371
372#endif
static __force_inline void hw_set_bits(io_rw_32 *addr, uint32_t mask)
Atomically set the specified bits to 1 in a HW register.
Definition address_mapped.h:121
static __force_inline void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask)
Set new values for a sub-set of the bits in a HW register.
Definition address_mapped.h:157
static __force_inline void hw_clear_bits(io_rw_32 *addr, uint32_t mask)
Atomically clear the specified bits to 0 in a HW register.
Definition address_mapped.h:131
static bool spi_is_writable(const spi_inst_t *spi)
Check whether a write can be done on SPI device.
Definition spi.h:232
static void spi_set_slave(spi_inst_t *spi, bool slave)
Set SPI master/slave.
Definition spi.h:209
static void spi_set_format(spi_inst_t *spi, uint data_bits, spi_cpol_t cpol, spi_cpha_t cpha, __unused spi_order_t order)
Configure SPI.
Definition spi.h:177
uint spi_init(spi_inst_t *spi, uint baudrate)
Initialise SPI instancesPuts the SPI into a known state, and enable it. Must be called before other f...
Definition spi.c:21
static bool spi_is_readable(const spi_inst_t *spi)
Check whether a read can be done on SPI device.
Definition spi.h:242
uint spi_set_baudrate(spi_inst_t *spi, uint baudrate)
Set SPI baudrate.
Definition spi.c:42
#define spi1
Definition spi.h:63
int spi_read_blocking(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, size_t len)
Read from an SPI device.
Definition spi.c:136
spi_cpol_t
Enumeration of SPI CPOL (clock polarity) values.
Definition spi.h:84
int spi_write_blocking(spi_inst_t *spi, const uint8_t *src, size_t len)
Write to an SPI device, blocking.
Definition spi.c:107
static bool spi_is_busy(const spi_inst_t *spi)
Check whether SPI is busy.
Definition spi.h:252
static uint spi_get_dreq(spi_inst_t *spi, bool is_tx)
Return the DREQ to use for pacing transfers to/from a particular SPI instance.
Definition spi.h:361
int spi_read16_blocking(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len)
Read from an SPI device.
Definition spi.c:203
static uint spi_get_index(const spi_inst_t *spi)
Convert SPI instance to hardware instance number.
Definition spi.h:151
spi_cpha_t
Enumeration of SPI CPHA (clock phase) values.
Definition spi.h:76
#define spi0
Definition spi.h:55
uint spi_get_baudrate(const spi_inst_t *spi)
Get SPI baudrate.
Definition spi.c:76
spi_order_t
Enumeration of SPI bit-order values.
Definition spi.h:92
int spi_write_read_blocking(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len)
Write/Read to/from an SPI device.
Definition spi.c:84
int spi_write16_blocking(spi_inst_t *spi, const uint16_t *src, size_t len)
Write to an SPI device.
Definition spi.c:178
int spi_write16_read16_blocking(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len)
Write/Read half words to/from an SPI device.
Definition spi.c:156
void spi_deinit(spi_inst_t *spi)
Deinitialise SPI instancesPuts the SPI into a disabled state. Init will need to be called to reenable...
Definition spi.c:36
struct spi_inst spi_inst_t
Definition spi.h:47
Definition spi.h:23