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ioqspi.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
3/*
4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _HARDWARE_STRUCTS_IOQSPI_H
10#define _HARDWARE_STRUCTS_IOQSPI_H
11
13#include "hardware/regs/io_qspi.h"
14
15// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
16//
17// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
18// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
19//
20// Bit-field descriptions are of the form:
21// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
22
23typedef struct {
24 _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
25 // GPIO status
26 // 0x04000000 [26] : IRQTOPROC (0): interrupt to processors, after override is applied
27 // 0x01000000 [24] : IRQFROMPAD (0): interrupt from pad before override is applied
28 // 0x00080000 [19] : INTOPERI (0): input signal to peripheral, after override is applied
29 // 0x00020000 [17] : INFROMPAD (0): input signal from pad, before override is applied
30 // 0x00002000 [13] : OETOPAD (0): output enable to pad after register override is applied
31 // 0x00001000 [12] : OEFROMPERI (0): output enable from selected peripheral, before register override is applied
32 // 0x00000200 [9] : OUTTOPAD (0): output signal to pad after register override is applied
33 // 0x00000100 [8] : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied
34 io_ro_32 status;
35
36 _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
37 // GPIO control including function select and overrides
38 // 0x30000000 [29:28] : IRQOVER (0)
39 // 0x00030000 [17:16] : INOVER (0)
40 // 0x00003000 [13:12] : OEOVER (0)
41 // 0x00000300 [9:8] : OUTOVER (0)
42 // 0x0000001f [4:0] : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table
43 io_rw_32 ctrl;
45
46typedef struct {
47 _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
48 // Interrupt Enable for proc0
49 // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0)
50 // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0)
51 // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0)
52 // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0)
53 // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0)
54 // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0)
55 // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0)
56 // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0)
57 // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0)
58 // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0)
59 // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0)
60 // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0)
61 // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0)
62 // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0)
63 // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0)
64 // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0)
65 // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0)
66 // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0)
67 // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0)
68 // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0)
69 // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0)
70 // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0)
71 // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
72 // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0)
73 io_rw_32 inte;
74
75 _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
76 // Interrupt Force for proc0
77 // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0)
78 // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0)
79 // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0)
80 // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0)
81 // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0)
82 // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0)
83 // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0)
84 // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0)
85 // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0)
86 // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0)
87 // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0)
88 // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0)
89 // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0)
90 // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0)
91 // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0)
92 // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0)
93 // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0)
94 // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0)
95 // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0)
96 // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0)
97 // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0)
98 // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0)
99 // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
100 // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0)
101 io_rw_32 intf;
102
103 _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
104 // Interrupt status after masking & forcing for proc0
105 // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0)
106 // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0)
107 // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0)
108 // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0)
109 // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0)
110 // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0)
111 // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0)
112 // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0)
113 // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0)
114 // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0)
115 // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0)
116 // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0)
117 // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0)
118 // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0)
119 // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0)
120 // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0)
121 // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0)
122 // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0)
123 // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0)
124 // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0)
125 // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0)
126 // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0)
127 // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
128 // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0)
129 io_ro_32 ints;
131
132typedef struct {
133 ioqspi_status_ctrl_hw_t io[NUM_QSPI_GPIOS]; // 6
134
135 _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
136 // Raw Interrupts
137 // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0)
138 // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0)
139 // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0)
140 // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0)
141 // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0)
142 // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0)
143 // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0)
144 // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0)
145 // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0)
146 // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0)
147 // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0)
148 // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0)
149 // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0)
150 // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0)
151 // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0)
152 // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0)
153 // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0)
154 // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0)
155 // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0)
156 // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0)
157 // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0)
158 // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0)
159 // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
160 // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0)
161 io_rw_32 intr;
162
163 io_qspi_ctrl_hw_t proc0_qspi_ctrl;
164
165 io_qspi_ctrl_hw_t proc1_qspi_ctrl;
166
167 io_qspi_ctrl_hw_t dormant_wake_qspi_ctrl;
169
170#define ioqspi_hw ((ioqspi_hw_t *)IO_QSPI_BASE)
171
172static_assert( NUM_QSPI_GPIOS == 6, "");
173
174#endif
Definition ioqspi.h:46
Definition ioqspi.h:132
Definition ioqspi.h:23