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usb.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
3/*
4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _HARDWARE_STRUCTS_USB_H
10#define _HARDWARE_STRUCTS_USB_H
11
13#include "hardware/regs/usb.h"
14
15// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb
16//
17// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
18// _REG_(x) will link to the corresponding register in hardware/regs/usb.h.
19//
20// Bit-field descriptions are of the form:
21// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
22
23// 0-15
24#define USB_NUM_ENDPOINTS 16
25
26// allow user to restrict number of endpoints available to save RAN
27#ifndef USB_MAX_ENDPOINTS
28#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS
29#endif
30
31// 1-15
32#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1)
33
34// Endpoint buffer control bits
35#define USB_BUF_CTRL_FULL 0x00008000u
36#define USB_BUF_CTRL_LAST 0x00004000u
37#define USB_BUF_CTRL_DATA0_PID 0x00000000u
38#define USB_BUF_CTRL_DATA1_PID 0x00002000u
39#define USB_BUF_CTRL_SEL 0x00001000u
40#define USB_BUF_CTRL_STALL 0x00000800u
41#define USB_BUF_CTRL_AVAIL 0x00000400u
42#define USB_BUF_CTRL_LEN_MASK 0x000003FFu
43#define USB_BUF_CTRL_LEN_LSB 0
44
45// ep_inout_ctrl bits
46#define EP_CTRL_ENABLE_BITS (1u << 31u)
47#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30)
48#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29)
49#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28)
50#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16)
51#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17)
52#define EP_CTRL_BUFFER_TYPE_LSB 26u
53#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u
54
55#define USB_DPRAM_SIZE 4096u
56
57// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb
58// Allow user to claim some of the USB RAM for themselves
59#ifndef USB_DPRAM_MAX
60#define USB_DPRAM_MAX USB_DPRAM_SIZE
61#endif
62
63// Define maximum packet sizes
64#define USB_MAX_ISO_PACKET_SIZE 1023
65#define USB_MAX_PACKET_SIZE 64
66
67typedef struct {
68 // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
69 volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
70
71 // Starts at ep1
73 io_rw_32 in;
74 io_rw_32 out;
75 } ep_ctrl[USB_NUM_ENDPOINTS - 1];
76
77 // Starts at ep0
79 io_rw_32 in;
80 io_rw_32 out;
81 } ep_buf_ctrl[USB_NUM_ENDPOINTS];
82
83 // EP0 buffers are fixed. Assumes single buffered mode for EP0
84 uint8_t ep0_buf_a[0x40];
85 uint8_t ep0_buf_b[0x40];
86
87 // Rest of DPRAM can be carved up as needed
88 uint8_t epx_data[USB_DPRAM_MAX - 0x180];
90
91static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, "");
92static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, "");
93
94typedef struct {
95 // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
96 volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
97
98 // Interrupt endpoint control 1 -> 15
100 io_rw_32 ctrl;
101 io_rw_32 spare;
102 } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
103
104 io_rw_32 epx_buf_ctrl;
105 io_rw_32 _spare0;
106
107 // Interrupt endpoint buffer control
109 io_rw_32 ctrl;
110 io_rw_32 spare;
111 } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
112
113 io_rw_32 epx_ctrl;
114
115 uint8_t _spare1[124];
116
117 // Should start at 0x180
118 uint8_t epx_data[USB_DPRAM_MAX - 0x180];
120
121static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, "");
122static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, "");
123
124typedef struct {
125 _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP
126 // Device address and endpoint control
127 // 0x000f0000 [19:16] : ENDPOINT (0): Device endpoint to send data to
128 // 0x0000007f [6:0] : ADDRESS (0): In device mode, the address that the device should respond to
129 io_rw_32 dev_addr_ctrl;
130
131 _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1
132 // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes)
133 //
134 // Interrupt endpoint 1
135 // 0x04000000 [26] : INTEP_PREAMBLE (0): Interrupt EP requires preamble (is a low speed device on a full speed hub)
136 // 0x02000000 [25] : INTEP_DIR (0): Direction of the interrupt endpoint
137 // 0x000f0000 [19:16] : ENDPOINT (0): Endpoint number of the interrupt endpoint
138 // 0x0000007f [6:0] : ADDRESS (0): Device address
139 io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; // 15
140
141 _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL
142 // Main control register
143 // 0x80000000 [31] : SIM_TIMING (0): Reduced timings for simulation
144 // 0x00000002 [1] : HOST_NDEVICE (0): Device mode = 0, Host mode = 1
145 // 0x00000001 [0] : CONTROLLER_EN (0): Enable controller
146 io_rw_32 main_ctrl;
147
148 _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR
149 // Set the SOF (Start of Frame) frame number in the host controller
150 // 0x000007ff [10:0] : COUNT (0)
151 io_wo_32 sof_rw;
152
153 _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD
154 // Read the last SOF (Start of Frame) frame number seen
155 // 0x000007ff [10:0] : COUNT (0)
156 io_ro_32 sof_rd;
157
158 _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL
159 // SIE control register
160 // 0x80000000 [31] : EP0_INT_STALL (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
161 // 0x40000000 [30] : EP0_DOUBLE_BUF (0): Device: EP0 single buffered = 0, double buffered = 1
162 // 0x20000000 [29] : EP0_INT_1BUF (0): Device: Set bit in BUFF_STATUS for every buffer completed on EP0
163 // 0x10000000 [28] : EP0_INT_2BUF (0): Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0
164 // 0x08000000 [27] : EP0_INT_NAK (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
165 // 0x04000000 [26] : DIRECT_EN (0): Direct bus drive enable
166 // 0x02000000 [25] : DIRECT_DP (0): Direct control of DP
167 // 0x01000000 [24] : DIRECT_DM (0): Direct control of DM
168 // 0x00040000 [18] : TRANSCEIVER_PD (0): Power down bus transceiver
169 // 0x00020000 [17] : RPU_OPT (0): Device: Pull-up strength (0=1K2, 1=2k3)
170 // 0x00010000 [16] : PULLUP_EN (0): Device: Enable pull up resistor
171 // 0x00008000 [15] : PULLDOWN_EN (0): Host: Enable pull down resistors
172 // 0x00002000 [13] : RESET_BUS (0): Host: Reset bus
173 // 0x00001000 [12] : RESUME (0): Device: Remote wakeup
174 // 0x00000800 [11] : VBUS_EN (0): Host: Enable VBUS
175 // 0x00000400 [10] : KEEP_ALIVE_EN (0): Host: Enable keep alive packet (for low speed bus)
176 // 0x00000200 [9] : SOF_EN (0): Host: Enable SOF generation (for full speed bus)
177 // 0x00000100 [8] : SOF_SYNC (0): Host: Delay packet(s) until after SOF
178 // 0x00000040 [6] : PREAMBLE_EN (0): Host: Preable enable for LS device on FS hub
179 // 0x00000010 [4] : STOP_TRANS (0): Host: Stop transaction
180 // 0x00000008 [3] : RECEIVE_DATA (0): Host: Receive transaction (IN to host)
181 // 0x00000004 [2] : SEND_DATA (0): Host: Send transaction (OUT from host)
182 // 0x00000002 [1] : SEND_SETUP (0): Host: Send Setup packet
183 // 0x00000001 [0] : START_TRANS (0): Host: Start transaction
184 io_rw_32 sie_ctrl;
185
186 _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS
187 // SIE status register
188 // 0x80000000 [31] : DATA_SEQ_ERROR (0): Data Sequence Error
189 // 0x40000000 [30] : ACK_REC (0): ACK received
190 // 0x20000000 [29] : STALL_REC (0): Host: STALL received
191 // 0x10000000 [28] : NAK_REC (0): Host: NAK received
192 // 0x08000000 [27] : RX_TIMEOUT (0): RX timeout is raised by both the host and device if an ACK is not received in...
193 // 0x04000000 [26] : RX_OVERFLOW (0): RX overflow is raised by the Serial RX engine if the incoming data is too fast
194 // 0x02000000 [25] : BIT_STUFF_ERROR (0): Bit Stuff Error
195 // 0x01000000 [24] : CRC_ERROR (0): CRC Error
196 // 0x00080000 [19] : BUS_RESET (0): Device: bus reset received
197 // 0x00040000 [18] : TRANS_COMPLETE (0): Transaction complete
198 // 0x00020000 [17] : SETUP_REC (0): Device: Setup packet received
199 // 0x00010000 [16] : CONNECTED (0): Device: connected
200 // 0x00000800 [11] : RESUME (0): Host: Device has initiated a remote resume
201 // 0x00000400 [10] : VBUS_OVER_CURR (0): VBUS over current detected
202 // 0x00000300 [9:8] : SPEED (0): Host: device speed
203 // 0x00000010 [4] : SUSPENDED (0): Bus in suspended state
204 // 0x0000000c [3:2] : LINE_STATE (0): USB bus line state
205 // 0x00000001 [0] : VBUS_DETECTED (0): Device: VBUS Detected
206 io_rw_32 sie_status;
207
208 _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL
209 // interrupt endpoint control register
210 // 0x0000fffe [15:1] : INT_EP_ACTIVE (0): Host: Enable interrupt endpoint 1 -> 15
211 io_rw_32 int_ep_ctrl;
212
213 _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS
214 // Buffer status register
215 // 0x80000000 [31] : EP15_OUT (0)
216 // 0x40000000 [30] : EP15_IN (0)
217 // 0x20000000 [29] : EP14_OUT (0)
218 // 0x10000000 [28] : EP14_IN (0)
219 // 0x08000000 [27] : EP13_OUT (0)
220 // 0x04000000 [26] : EP13_IN (0)
221 // 0x02000000 [25] : EP12_OUT (0)
222 // 0x01000000 [24] : EP12_IN (0)
223 // 0x00800000 [23] : EP11_OUT (0)
224 // 0x00400000 [22] : EP11_IN (0)
225 // 0x00200000 [21] : EP10_OUT (0)
226 // 0x00100000 [20] : EP10_IN (0)
227 // 0x00080000 [19] : EP9_OUT (0)
228 // 0x00040000 [18] : EP9_IN (0)
229 // 0x00020000 [17] : EP8_OUT (0)
230 // 0x00010000 [16] : EP8_IN (0)
231 // 0x00008000 [15] : EP7_OUT (0)
232 // 0x00004000 [14] : EP7_IN (0)
233 // 0x00002000 [13] : EP6_OUT (0)
234 // 0x00001000 [12] : EP6_IN (0)
235 // 0x00000800 [11] : EP5_OUT (0)
236 // 0x00000400 [10] : EP5_IN (0)
237 // 0x00000200 [9] : EP4_OUT (0)
238 // 0x00000100 [8] : EP4_IN (0)
239 // 0x00000080 [7] : EP3_OUT (0)
240 // 0x00000040 [6] : EP3_IN (0)
241 // 0x00000020 [5] : EP2_OUT (0)
242 // 0x00000010 [4] : EP2_IN (0)
243 // 0x00000008 [3] : EP1_OUT (0)
244 // 0x00000004 [2] : EP1_IN (0)
245 // 0x00000002 [1] : EP0_OUT (0)
246 // 0x00000001 [0] : EP0_IN (0)
247 io_rw_32 buf_status;
248
249 _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE
250 // Which of the double buffers should be handled
251 // 0x80000000 [31] : EP15_OUT (0)
252 // 0x40000000 [30] : EP15_IN (0)
253 // 0x20000000 [29] : EP14_OUT (0)
254 // 0x10000000 [28] : EP14_IN (0)
255 // 0x08000000 [27] : EP13_OUT (0)
256 // 0x04000000 [26] : EP13_IN (0)
257 // 0x02000000 [25] : EP12_OUT (0)
258 // 0x01000000 [24] : EP12_IN (0)
259 // 0x00800000 [23] : EP11_OUT (0)
260 // 0x00400000 [22] : EP11_IN (0)
261 // 0x00200000 [21] : EP10_OUT (0)
262 // 0x00100000 [20] : EP10_IN (0)
263 // 0x00080000 [19] : EP9_OUT (0)
264 // 0x00040000 [18] : EP9_IN (0)
265 // 0x00020000 [17] : EP8_OUT (0)
266 // 0x00010000 [16] : EP8_IN (0)
267 // 0x00008000 [15] : EP7_OUT (0)
268 // 0x00004000 [14] : EP7_IN (0)
269 // 0x00002000 [13] : EP6_OUT (0)
270 // 0x00001000 [12] : EP6_IN (0)
271 // 0x00000800 [11] : EP5_OUT (0)
272 // 0x00000400 [10] : EP5_IN (0)
273 // 0x00000200 [9] : EP4_OUT (0)
274 // 0x00000100 [8] : EP4_IN (0)
275 // 0x00000080 [7] : EP3_OUT (0)
276 // 0x00000040 [6] : EP3_IN (0)
277 // 0x00000020 [5] : EP2_OUT (0)
278 // 0x00000010 [4] : EP2_IN (0)
279 // 0x00000008 [3] : EP1_OUT (0)
280 // 0x00000004 [2] : EP1_IN (0)
281 // 0x00000002 [1] : EP0_OUT (0)
282 // 0x00000001 [0] : EP0_IN (0)
283 io_ro_32 buf_cpu_should_handle;
284
285 _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT
286 // Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer
287 // 0x80000000 [31] : EP15_OUT (0)
288 // 0x40000000 [30] : EP15_IN (0)
289 // 0x20000000 [29] : EP14_OUT (0)
290 // 0x10000000 [28] : EP14_IN (0)
291 // 0x08000000 [27] : EP13_OUT (0)
292 // 0x04000000 [26] : EP13_IN (0)
293 // 0x02000000 [25] : EP12_OUT (0)
294 // 0x01000000 [24] : EP12_IN (0)
295 // 0x00800000 [23] : EP11_OUT (0)
296 // 0x00400000 [22] : EP11_IN (0)
297 // 0x00200000 [21] : EP10_OUT (0)
298 // 0x00100000 [20] : EP10_IN (0)
299 // 0x00080000 [19] : EP9_OUT (0)
300 // 0x00040000 [18] : EP9_IN (0)
301 // 0x00020000 [17] : EP8_OUT (0)
302 // 0x00010000 [16] : EP8_IN (0)
303 // 0x00008000 [15] : EP7_OUT (0)
304 // 0x00004000 [14] : EP7_IN (0)
305 // 0x00002000 [13] : EP6_OUT (0)
306 // 0x00001000 [12] : EP6_IN (0)
307 // 0x00000800 [11] : EP5_OUT (0)
308 // 0x00000400 [10] : EP5_IN (0)
309 // 0x00000200 [9] : EP4_OUT (0)
310 // 0x00000100 [8] : EP4_IN (0)
311 // 0x00000080 [7] : EP3_OUT (0)
312 // 0x00000040 [6] : EP3_IN (0)
313 // 0x00000020 [5] : EP2_OUT (0)
314 // 0x00000010 [4] : EP2_IN (0)
315 // 0x00000008 [3] : EP1_OUT (0)
316 // 0x00000004 [2] : EP1_IN (0)
317 // 0x00000002 [1] : EP0_OUT (0)
318 // 0x00000001 [0] : EP0_IN (0)
319 io_rw_32 abort;
320
321 _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE
322 // Device only: Used in conjunction with `EP_ABORT`
323 // 0x80000000 [31] : EP15_OUT (0)
324 // 0x40000000 [30] : EP15_IN (0)
325 // 0x20000000 [29] : EP14_OUT (0)
326 // 0x10000000 [28] : EP14_IN (0)
327 // 0x08000000 [27] : EP13_OUT (0)
328 // 0x04000000 [26] : EP13_IN (0)
329 // 0x02000000 [25] : EP12_OUT (0)
330 // 0x01000000 [24] : EP12_IN (0)
331 // 0x00800000 [23] : EP11_OUT (0)
332 // 0x00400000 [22] : EP11_IN (0)
333 // 0x00200000 [21] : EP10_OUT (0)
334 // 0x00100000 [20] : EP10_IN (0)
335 // 0x00080000 [19] : EP9_OUT (0)
336 // 0x00040000 [18] : EP9_IN (0)
337 // 0x00020000 [17] : EP8_OUT (0)
338 // 0x00010000 [16] : EP8_IN (0)
339 // 0x00008000 [15] : EP7_OUT (0)
340 // 0x00004000 [14] : EP7_IN (0)
341 // 0x00002000 [13] : EP6_OUT (0)
342 // 0x00001000 [12] : EP6_IN (0)
343 // 0x00000800 [11] : EP5_OUT (0)
344 // 0x00000400 [10] : EP5_IN (0)
345 // 0x00000200 [9] : EP4_OUT (0)
346 // 0x00000100 [8] : EP4_IN (0)
347 // 0x00000080 [7] : EP3_OUT (0)
348 // 0x00000040 [6] : EP3_IN (0)
349 // 0x00000020 [5] : EP2_OUT (0)
350 // 0x00000010 [4] : EP2_IN (0)
351 // 0x00000008 [3] : EP1_OUT (0)
352 // 0x00000004 [2] : EP1_IN (0)
353 // 0x00000002 [1] : EP0_OUT (0)
354 // 0x00000001 [0] : EP0_IN (0)
355 io_rw_32 abort_done;
356
357 _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM
358 // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0
359 // 0x00000002 [1] : EP0_OUT (0)
360 // 0x00000001 [0] : EP0_IN (0)
361 io_rw_32 ep_stall_arm;
362
363 _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL
364 // Used by the host controller
365 // 0x03ff0000 [25:16] : DELAY_FS (0x10): NAK polling interval for a full speed device
366 // 0x000003ff [9:0] : DELAY_LS (0x10): NAK polling interval for a low speed device
367 io_rw_32 nak_poll;
368
369 _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK
370 // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set
371 // 0x80000000 [31] : EP15_OUT (0)
372 // 0x40000000 [30] : EP15_IN (0)
373 // 0x20000000 [29] : EP14_OUT (0)
374 // 0x10000000 [28] : EP14_IN (0)
375 // 0x08000000 [27] : EP13_OUT (0)
376 // 0x04000000 [26] : EP13_IN (0)
377 // 0x02000000 [25] : EP12_OUT (0)
378 // 0x01000000 [24] : EP12_IN (0)
379 // 0x00800000 [23] : EP11_OUT (0)
380 // 0x00400000 [22] : EP11_IN (0)
381 // 0x00200000 [21] : EP10_OUT (0)
382 // 0x00100000 [20] : EP10_IN (0)
383 // 0x00080000 [19] : EP9_OUT (0)
384 // 0x00040000 [18] : EP9_IN (0)
385 // 0x00020000 [17] : EP8_OUT (0)
386 // 0x00010000 [16] : EP8_IN (0)
387 // 0x00008000 [15] : EP7_OUT (0)
388 // 0x00004000 [14] : EP7_IN (0)
389 // 0x00002000 [13] : EP6_OUT (0)
390 // 0x00001000 [12] : EP6_IN (0)
391 // 0x00000800 [11] : EP5_OUT (0)
392 // 0x00000400 [10] : EP5_IN (0)
393 // 0x00000200 [9] : EP4_OUT (0)
394 // 0x00000100 [8] : EP4_IN (0)
395 // 0x00000080 [7] : EP3_OUT (0)
396 // 0x00000040 [6] : EP3_IN (0)
397 // 0x00000020 [5] : EP2_OUT (0)
398 // 0x00000010 [4] : EP2_IN (0)
399 // 0x00000008 [3] : EP1_OUT (0)
400 // 0x00000004 [2] : EP1_IN (0)
401 // 0x00000002 [1] : EP0_OUT (0)
402 // 0x00000001 [0] : EP0_IN (0)
403 io_rw_32 ep_nak_stall_status;
404
405 _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING
406 // Where to connect the USB controller
407 // 0x00000008 [3] : SOFTCON (0)
408 // 0x00000004 [2] : TO_DIGITAL_PAD (0)
409 // 0x00000002 [1] : TO_EXTPHY (0)
410 // 0x00000001 [0] : TO_PHY (0)
411 io_rw_32 muxing;
412
413 _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR
414 // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO
415 // 0x00000020 [5] : OVERCURR_DETECT_EN (0)
416 // 0x00000010 [4] : OVERCURR_DETECT (0)
417 // 0x00000008 [3] : VBUS_DETECT_OVERRIDE_EN (0)
418 // 0x00000004 [2] : VBUS_DETECT (0)
419 // 0x00000002 [1] : VBUS_EN_OVERRIDE_EN (0)
420 // 0x00000001 [0] : VBUS_EN (0)
421 io_rw_32 pwr;
422
423 _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT
424 // This register allows for direct control of the USB phy
425 // 0x00400000 [22] : DM_OVV (0): DM over voltage
426 // 0x00200000 [21] : DP_OVV (0): DP over voltage
427 // 0x00100000 [20] : DM_OVCN (0): DM overcurrent
428 // 0x00080000 [19] : DP_OVCN (0): DP overcurrent
429 // 0x00040000 [18] : RX_DM (0): DPM pin state
430 // 0x00020000 [17] : RX_DP (0): DPP pin state
431 // 0x00010000 [16] : RX_DD (0): Differential RX
432 // 0x00008000 [15] : TX_DIFFMODE (0): TX_DIFFMODE=0: Single ended mode
433 // 0x00004000 [14] : TX_FSSLEW (0): TX_FSSLEW=0: Low speed slew rate
434 // 0x00002000 [13] : TX_PD (0): TX power down override (if override enable is set)
435 // 0x00001000 [12] : RX_PD (0): RX power down override (if override enable is set)
436 // 0x00000800 [11] : TX_DM (0): Output data
437 // 0x00000400 [10] : TX_DP (0): Output data
438 // 0x00000200 [9] : TX_DM_OE (0): Output enable
439 // 0x00000100 [8] : TX_DP_OE (0): Output enable
440 // 0x00000040 [6] : DM_PULLDN_EN (0): DM pull down enable
441 // 0x00000020 [5] : DM_PULLUP_EN (0): DM pull up enable
442 // 0x00000010 [4] : DM_PULLUP_HISEL (0): Enable the second DM pull up resistor
443 // 0x00000004 [2] : DP_PULLDN_EN (0): DP pull down enable
444 // 0x00000002 [1] : DP_PULLUP_EN (0): DP pull up enable
445 // 0x00000001 [0] : DP_PULLUP_HISEL (0): Enable the second DP pull up resistor
446 io_rw_32 phy_direct;
447
448 _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE
449 // Override enable for each control in usbphy_direct
450 // 0x00008000 [15] : TX_DIFFMODE_OVERRIDE_EN (0)
451 // 0x00001000 [12] : DM_PULLUP_OVERRIDE_EN (0)
452 // 0x00000800 [11] : TX_FSSLEW_OVERRIDE_EN (0)
453 // 0x00000400 [10] : TX_PD_OVERRIDE_EN (0)
454 // 0x00000200 [9] : RX_PD_OVERRIDE_EN (0)
455 // 0x00000100 [8] : TX_DM_OVERRIDE_EN (0)
456 // 0x00000080 [7] : TX_DP_OVERRIDE_EN (0)
457 // 0x00000040 [6] : TX_DM_OE_OVERRIDE_EN (0)
458 // 0x00000020 [5] : TX_DP_OE_OVERRIDE_EN (0)
459 // 0x00000010 [4] : DM_PULLDN_EN_OVERRIDE_EN (0)
460 // 0x00000008 [3] : DP_PULLDN_EN_OVERRIDE_EN (0)
461 // 0x00000004 [2] : DP_PULLUP_EN_OVERRIDE_EN (0)
462 // 0x00000002 [1] : DM_PULLUP_HISEL_OVERRIDE_EN (0)
463 // 0x00000001 [0] : DP_PULLUP_HISEL_OVERRIDE_EN (0)
464 io_rw_32 phy_direct_override;
465
466 _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM
467 // Used to adjust trim values of USB phy pull down resistors
468 // 0x00001f00 [12:8] : DM_PULLDN_TRIM (0x1f): Value to drive to USB PHY
469 // 0x0000001f [4:0] : DP_PULLDN_TRIM (0x1f): Value to drive to USB PHY
470 io_rw_32 phy_trim;
471
472 uint32_t _pad0;
473
474 _REG_(USB_INTR_OFFSET) // USB_INTR
475 // Raw Interrupts
476 // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
477 // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
478 // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
479 // 0x00010000 [16] : SETUP_REQ (0): Device
480 // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
481 // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes
482 // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes
483 // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS
484 // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS
485 // 0x00000400 [10] : STALL (0): Source: SIE_STATUS
486 // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS
487 // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS
488 // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
489 // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
490 // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS
491 // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
492 // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS
493 // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
494 // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host
495 // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
496 io_ro_32 intr;
497
498 _REG_(USB_INTE_OFFSET) // USB_INTE
499 // Interrupt Enable
500 // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
501 // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
502 // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
503 // 0x00010000 [16] : SETUP_REQ (0): Device
504 // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
505 // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes
506 // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes
507 // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS
508 // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS
509 // 0x00000400 [10] : STALL (0): Source: SIE_STATUS
510 // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS
511 // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS
512 // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
513 // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
514 // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS
515 // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
516 // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS
517 // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
518 // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host
519 // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
520 io_rw_32 inte;
521
522 _REG_(USB_INTF_OFFSET) // USB_INTF
523 // Interrupt Force
524 // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
525 // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
526 // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
527 // 0x00010000 [16] : SETUP_REQ (0): Device
528 // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
529 // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes
530 // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes
531 // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS
532 // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS
533 // 0x00000400 [10] : STALL (0): Source: SIE_STATUS
534 // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS
535 // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS
536 // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
537 // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
538 // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS
539 // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
540 // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS
541 // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
542 // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host
543 // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
544 io_rw_32 intf;
545
546 _REG_(USB_INTS_OFFSET) // USB_INTS
547 // Interrupt status after masking & forcing
548 // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
549 // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
550 // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
551 // 0x00010000 [16] : SETUP_REQ (0): Device
552 // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
553 // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes
554 // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes
555 // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS
556 // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS
557 // 0x00000400 [10] : STALL (0): Source: SIE_STATUS
558 // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS
559 // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS
560 // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
561 // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
562 // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS
563 // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
564 // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS
565 // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
566 // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host
567 // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
568 io_ro_32 ints;
569} usb_hw_t;
570
571#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE)
572
573#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE)
574#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE)
575
576static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, "");
577
578#endif
Definition usb.h:67
Definition usb.h:94
Definition usb.h:124